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User:Wilsonjd/IBM Telum II

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Telum II
General information
Launched2025
Designed byIBM
Common manufacturer
Performance
Max. CPU clock rate5.5 GHz
Physical specifications
Cores
  • 8
Cache
L2 cache10 x 36 MB
L3 cache360 MB virtual L3
L4 cache2.8 GB virtual L4
Architecture and classification
Technology node5 nm
Instruction setz/Architecture
History
PredecessorTelum
Both sides of the Telum microprocessor

Telum II is a microprocessor made by IBM for the IBM z17 series mainframe computers.[2][3] The processor was announced at the Hot Chips 2024 conference on 26 August 2024.[2] Telum ** features advanced on-processor chip acceleration for artificial intelligence inferencing while a transaction is taking place.[clarification needed][4][5]

Description

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The chip contains 8 processor cores with a deep superscalar out-of-order pipeline, running at 5.5 GHz clock frequency which is optimized for the demands of heterogenous enterprise-class workloads (e.g: finance, security sensitive applications, applications requiring extreme reliability). The cache and chip-interconnection infrastructure provides 10 36 MB L2 cache and can scale to 32 Telum chips.[6][3][7] The cache design has been described as "revolutionary" in 2021,[6] by creating a system where the L2 cache of one core can be used as virtual L3 and L4 caches for another core.[3][1] The Telum processor can either be water cooled or air cooled, but water cooling is required for running more than a few Telum processors in a single IBM compute drawer.[8][9] Unlike other processors, the IBM Telum does not thermal throttle by reducing clock speed; instead it inserts sleep state instructions.[8][9]

Telum adds a new, NNP-Data-Type-1 Format, 16-bit floating point format and several new instructions. The Neural Network Processing Assists (NNPA)[10] instruction performs a variety of tensor instructions useful for neural networks.

See also

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References

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  1. 1 2 Cite error: The named reference 2023-07-24-ars was invoked but never defined (see the help page).
  2. 1 2 Cite error: The named reference 2021-08-23-forbes was invoked but never defined (see the help page).
  3. 1 2 3 Cite error: The named reference 2022-04-29-ieee-spectrum was invoked but never defined (see the help page).
  4. ↑ Cite error: The named reference 2021-08-24-techrepublic was invoked but never defined (see the help page).
  5. ↑ Cite error: The named reference 2021-08-26-sce was invoked but never defined (see the help page).
  6. 1 2 Cite error: The named reference 2021-09-02-anandtech was invoked but never defined (see the help page).
  7. ↑ Cite error: The named reference 2022-04-05-yt-ltt was invoked but never defined (see the help page).
  8. 1 2 IBM z17 Technical Introduction (PDF) (First ed.). IBM. April 2025. SG24-8580-01.
  9. 1 2 Why Do Mainframes Still Exist? What's Inside One? 40TB, 200+ Cores, AI, and more!, 28 October 2023, retrieved 2024-01-11
  10. ↑ "NEURAL NETWORK PROCESSING ASSIST" (PDF). z/Architecture Principles of Operation (PDF) (Fourteenth ed.). IBM. May 2022. pp. 26-61 – 26-96. SA22-7832-13. Retrieved March 31, 2025.
  11. {{Cite news |last=Jacobi |first=Christian |title=New Telum II Processor and IBM Spyre Accelerator: Expanding AI on IBM Z and IBM LinuxONE |url=https://www.ibm.com/new/announcements/telum-ii |access-date=14 Nov 2025 |date=08 Sept 2024 |website=IBM |language=en}
  12. {{Cite web |last=Lam |first=Chester |date=08 Sept 2024 |title=Telum II at Hot Chips 2024: Mainframe with a Unique Caching Strategy |url=https://chipsandcheese.com/p/telum-ii-at-hot-chips-2024-mainframe-with-a-unique-caching-strategy |access-date=14 Nov 2025 |website=chipsandcheese |language=en }
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